1. Technical Field
The present invention relates to power saving in a programmable device.
2. Background Art
In recent years, a dynamic reconfigurable device has been developed that can change a configuration in a short time such as from several microseconds to several nanoseconds, even when operating (see non-patent document 1).
When the device is made to be more high-speed and miniaturized, there is a problem of leaked power, which takes up as much as approximately 50% of the total consumed energy of a chip.
As a measure against this problem, a technology is disclosed in patent document 1, in which power gating technology is applied and power supply is cut off to any circuit block that is not assigned a function and is unused, or is in a wait state.
Patent document 1: U.S. Pat. No. 7,098,689
Non-patent document 1: Masato Motomura, “A Dynamically Reconfigurable Processor Architecture”, Microprocessor Forum, October 2002
However, in the above-described technology, there is the following issue. When a power supply to a circuit block in a wait state, for which operation has been temporarily stopped, is cut off to conserve energy, operations of the circuit block, including configuration information that defines the operations of the circuit block, are lost from an SRAM (Static Random Access Memory) and it is necessary to set the configuration information again the next time that power is supplied. Therefore, restarting operation from a pre-standby state cannot be performed immediately.
In view of the above issue, an object of the present invention is to provide a programmable device capable of saving power by performing high-speed power supply cut off control in which the internal state is not lost when the power supply is cut off.
In order to solve the above problem, the present invention is a programmable device including one or more processing tiles including a core logic unit that performs a calculation indicated by circuit information, and a configuration memory that stores the circuit information to be set in the core logic unit; a power supply unit operable to supply power to the core logic units and the configuration memories; and a control unit operable to, for each of the one or more processing tiles, when the processing tile is unused, cut off a power supply route to the core logic unit that is separate from a power supply route to the configuration memory.